T3-4 - Front-End and Nodes Architectures
AUREIS Thrusts 3–4 develop the hardware and communication fabric needed to implement intelligent sensing at extreme rates and constrained power. This includes trainable/adaptive front-end ASIC architectures, combined analog + digital edge computing options, and communication strategies for dense multi-tile systems so that information can be extracted early without overwhelming bandwidth or cooling budgets.
Traditional designs optimize each layer independently (sensor → front end → processing → storage). AUREIS pushes toward closed-loop adaptive systems, where front-end parameters, on-node processing, and even data representation can be adjusted based on incoming data and scientific intent. This includes exploring parametric analog interfaces and architectures that can be co-trained with downstream models to maximize fidelity while improving energy efficiency and reducing unnecessary data movement.
- Trainable front-end ASIC architectures with adaptive analog interfaces and reconfigurable signal conditioning
- Analog + digital edge computing co-design, including in-memory/analog compute concepts where appropriate
- Early correction and preprocessing (e.g., baseline/gain normalization and tile-local transforms) to enable earlier inference/compression
- Dense tiled-system communication and inter-tile/inter-node strategies, including event-driven and meshed/hierarchical approaches
- Programmable/reconfigurable logic strategies (FPGAs, eFPGA-like concepts, and heterogeneous coprocessors) for updating models and algorithms during experiments
Interfaces: T3–4 implements the compute/communication structures needed by T1–2 workflows, and incorporates sensor constraints and operating envelopes coming from T5.
Outputs: prototype architecture concepts and building blocks, evaluation results, and released talks/papers linked via Workshops & Publications.
